Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC. Nevertheless, there are many factors that make the continued miniaturization of ICs difficult. For example, as the size of vias (or pathways between integrated circuit layers used to electrically connect separate conductive layers) decreases, electrical resistance increases.
Conventional integrated circuits utilize vias to connect structures (e.g., gates, drain regions, source regions) and conductive lines. For example, a via can connect a gate above the substrate to a conductor line in the metal 1 layer. Vias can also interconnect conductive lines. For example, a via can connect a conductive line in a metal 1 layer to a conductor line in a metal 2 layer. A via is typically a metal plug which extends through an insulative layer in a multilayer integrated circuit. Vias and barrier layers are discussed in U.S. Pat. Nos. 5,646,448; 5,770,519; and 5,639,691; each of which are assigned to the assignee of the present application.
A barrier layer is used to protect the via and insulative layer from metal diffusion and the via and conductive line from electromigration (EM). The barrier layer can contribute significantly to resistance associated with the via metal. Electromigration is the mass transport due to momentum exchange between conducting electrons and diffusing metal atoms. Electromigration causes progressive damage to the metal conductors in an integrated circuit. In general, metals are most susceptible to electromigration at very high current density and temperatures of 100° C. or more.
Integrated circuit manufacturers have attempted to reduce via resistance as the via size decreases by reducing the thickness of the barrier material. According to a conventional physical vapor deposition (PVD) process, IC manufacturers deposit a very thin barrier material at the bottom of the via due to non-conformal deposition. The thickness of the barrier material is reduced by chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. These advanced deposition processes form highly conformal barrier metal films of relatively small thickness. However, reducing the barrier thickness causes the barrier to become more permeable to copper (Cu) diffusion, which can adversely affect resistance to electromigration.
Electromigration failures have been described by Stanley Wolf, Ph.D. in Silicon Processing for the VLSI Era, Lattice Press, Sunset Beach, Calif., Vol. 2, pp. 264–65 (1990). Dr. Wolf explains that a positive divergence of the motion of the ions of a conductor leads to an accumulation of vacancies, forming a void in the metal. Such voids may ultimately grow to a size that results in open-circuit failure of the conductor line.
A seed layer can be used to help electroplate Cu from an electrolyte solution onto vias and trenches with full Cu fill without voids. Generally, the Cu seed can be sputtered from a manufactured solid Cu targets. However, the manufacture of some Cu-alloy solid targets can be difficult due to poor metallurgical and mechanical properties of the resulting solid target. The alloying elements may not be uniformly incorporated or may be in a non-pure form which results in poor target erosion and insufficient concentration in the seed layer.
Thus, there is a need for a method of ion implantation to form alloy layers in copper. Further, there is a need for a method of forming a seed layer without manufacturing copper alloy targets. Even further, there is a need for implanting elements into seed layer using a low energy ion implantation process.